Simulation of DSP algorithms on fixed point architectures

This paper presents software tools to simulate DSP algorithms on a wide variety of fixed point architectures including microprocessors, DSPs and FPGA devices. Existing solutions for evaluating the signal quality in fixed point algorithms are either unable to deal with non-linear systems, fail to consider the architectural details of the target device or do not produce a real output that can be used in subjective testing. Using example non-linear algorithms it is shown that architectural details must be considered when evaluating numerical performance.