An assembly source level global compacter for digital signal processors

Author

Kafka, Stephen

Author_Institution

Analog Devices Inc., Norwood, MA, USA

fYear

1990

fDate

3-6 Apr 1990

Firstpage

1061

Abstract

A global compacter is presented for digital signal processors. The global compaction algorithm outlined demonstrates that optimal or near-optimal code can be produced for digital signal processing (DSP) chips by employing conventional compiler optimization techniques in conjunction with a global compacter and a loop pipeliner. Code can be efficiently compacted across basic block boundaries as well as within basic blocks. The loop pipeliner produces optimal or near-optimal pipelined loops for any looping structure. The global compacter can be used by both high-level-language compilers and hand assemblers

Keywords

computerised signal processing; digital signal processing chips; program assemblers; program compilers; DSP chips; assembly source level; compiler optimization techniques; digital signal processing; digital signal processors; global compacter; global compaction algorithm; hand assemblers; high-level-language compilers; loop pipeliner; Assembly; Compaction; Data analysis; Digital signal processing; Digital signal processing chips; Digital signal processors; High level languages; Optimizing compilers; Pipeline processing; Signal processing algorithms; VLIW;

fLanguage

English

Publisher

ieee

Conference_Titel

Acoustics, Speech, and Signal Processing, 1990. ICASSP-90., 1990 International Conference on

Conference_Location

Albuquerque, NM

ISSN

1520-6149

Type

conf

DOI

10.1109/ICASSP.1990.116099

Filename

116099