A new reconfigurable bit-serial systolic divider for GF(2^m) and GF(p)

Author

Cohen, Aaron E. ; Parhi, Keshab K.

Author_Institution

Dept. of Electr. & Comput. Eng., Univ. of Minnesota Twin Cities, MN, USA

Volume

5

fYear

2005

fDate

18-23 March 2005

Abstract

The paper focuses on the design of a new dual field divider that can achieve performance of 1/m throughput. This dual field division unit can operate at 118 MHz with a latency of 7m-2 cycles and has an area requirement 15 XOR2, 40 AND2, 29 MUX2, and 7 INV gates per processing element with a total of 2m processing elements. It is intended to be used in an elliptic curve crypto-accelerator for GF(2^m) and GF(p). The actual performance for scalar point multiplication in GF(2⁵⁷¹) running at 100 MHz would be 20.4 kP/s. The actual performance for scalar point multiplication in GF(p) with |p| = 521 running at 100 MHz would be 24.4 kP/s.

Keywords

Galois fields; digital arithmetic; dividing circuits; public key cryptography; systolic arrays; 100 MHz; 118 MHz; Galois fields; dual field divider; dual field division unit; elliptic curve crypto-accelerator; elliptic curve cryptography; latency; public key cryptosystems; reconfigurable bit-serial systolic divider; scalar point multiplication; systolic array; throughput; Cities and towns; Delay; Elliptic curve cryptography; Hardware; Large-scale systems; Public key cryptography; Security; Switches; Systolic arrays; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Acoustics, Speech, and Signal Processing, 2005. Proceedings. (ICASSP '05). IEEE International Conference on

ISSN

1520-6149

Print_ISBN

0-7803-8874-7

Type

conf

DOI

10.1109/ICASSP.2005.1416251

Filename

1416251

A new reconfigurable bit-serial systolic divider for GF(2m) and GF(p)

Cohen, Aaron E. ; Parhi, Keshab K.

conf

A new reconfigurable bit-serial systolic divider for GF(2^m) and GF(p)