Design of a flexible VLSI architecture for M-channel filter bank lifting factorizations

We present an efficient VLSI architecture focusing on M-channel multirate filter banks using the lifting scheme. Since the M-channel lifting factorization results in a signal flow graph with a variable structure, the architecture must have a high degree of flexibility to allow the implementation of basically different lifting factorizations. The proposed architecture is convenient to realize arbitrary lifting factorizations on a variable amount of arithmetic resources, leading to an adaptability for the real-time requirements of various DSP applications.