• DocumentCode
    2946767
  • Title

    Fg-STP: Fine-Grain Single Thread Partitioning on Multicores

  • Author

    Ranjan, Rakesh ; Latorre, Fernando ; Marcuello, Pedro ; Gonzalez, Antonio

  • Author_Institution
    Intel Barcelona Res. Center, Barcelona, Spain
  • fYear
    2011
  • fDate
    12-16 Feb. 2011
  • Firstpage
    15
  • Lastpage
    24
  • Abstract
    Power and complexity issues have led the microprocessor industry to shift to Chip Multiprocessors in order to be able to better utilize the additional transistors ensured by Moore´s law. While parallel programs are going to be able to take most of the advantage of these CMPs, single thread applications are not equipped to benefit from them. In this paper we propose Fine-Grain Single-Thread Partitioning (Fg-STP), a hardware-only scheme that takes advantage of CMP designs to speedup single-threaded applications. Our proposal improves single thread performance by reconfiguring two cores with the aim of collaborating on the fetching and execution of the instructions. These cores are basically conventional out-of-order cores in which execution is orchestrated using a dedicated hardware that has minimum and localized impact on the original design of the cores. This approach partitions the code at instruction granularity and differs from previous proposals on the extensive use of dependence speculation, replication and communication. These features are combined with the ability to look for parallelism on large instruction windows without any software intervention (no re-compilation or profiling hints are needed). These characteristics allow Fg-STP to speedup single thread by 18% and 7% on average over similar hardware-only approaches like Core Fusion, on medium sized and small sized 2-core CMP respectively for Spec 2006 benchmarks.
  • Keywords
    multiprocessing systems; parallel processing; CMP; Fg-STP; Moore law; chip multiprocessor; fine grain single thread partitioning; multicore system; parallel program; Hardware; Multicore processing; Out of order; Proposals; Tiles;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    High Performance Computer Architecture (HPCA), 2011 IEEE 17th International Symposium on
  • Conference_Location
    San Antonio, TX
  • ISSN
    1530-0897
  • Print_ISBN
    978-1-4244-9432-3
  • Type

    conf

  • DOI
    10.1109/HPCA.2011.5749713
  • Filename
    5749713