• DocumentCode
    2946919
  • Title

    MOPED: Orchestrating interprocess message data on CMPs

  • Author

    Gu, Junli ; Lumetta, Steven S. ; Kumar, Rakesh ; Sun, Yihe

  • Author_Institution
    Inst. of Microelectron., Tsinghua Univ., Beijing, China
  • fYear
    2011
  • fDate
    12-16 Feb. 2011
  • Firstpage
    111
  • Lastpage
    120
  • Abstract
    Future CMPs will combine many simple cores with deep cache hierarchies. With more cores, cache resources per core are fewer, and must be shared carefully to avoid poor utilization due to conflicts and pollution. Explicit motion of data in these architectures, such as message passing, can provide hints about program behavior that can be used to hide latency and improve cache behavior. However, to make these models attractive, synchronization overhead and data copying must also be offloaded from the processors. In this paper, we describe a Message Orchestration and Performance Enhancement Device (MOPED) that provides hardware mechanisms to support state-of-the-art message passing protocols such as MPI. MOPED extends the per-processor cache controllers and coherence protocol to support message synchronization and management in hardware, to transfer message data efficiently without intermediate buffer copies, and to place useful data in caches in a timely manner. MOPED thus allows full overlap between communication and computation on the cores. We extended a 16-core full-system simulator based on Simics and FeS2. MOPED interacts with the directory controllers to orchestrate message data. We evaluated benefits to performance and coherence traffic by integrating MOPED into the MPICH runtime. Relative to unmodified MPI execution, MOPED reduces execution time of real applications (NAS Parallel Benchmarks) by 17-45% and of communication microbenchmarks (Intel´s IMB) by 76-94%. Off-chip memory misses are reduced by 43-88% for applications and by 75-100% for microbenchmarks.
  • Keywords
    cache storage; message passing; microprocessor chips; multiprocessing systems; FeS2 simulator; MOPED device; Simics simulator; cache hierarchy; chip multiprocessors; message data interprocessing; message orchestration and performance enhancement device; message passing interface; message passing protocols; message synchronization; Coherence; Hardware; Message passing; Motorcycles; Program processors; Protocols; Synchronization;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    High Performance Computer Architecture (HPCA), 2011 IEEE 17th International Symposium on
  • Conference_Location
    San Antonio, TX
  • ISSN
    1530-0897
  • Print_ISBN
    978-1-4244-9432-3
  • Type

    conf

  • DOI
    10.1109/HPCA.2011.5749721
  • Filename
    5749721