Title :
An area-optimized solution to introduce redundant arithmetic in high-level synthesis
Author_Institution :
Lab. LIP, Ecole Normale Superieure de Lyon, France
Abstract :
It is currently possible to create a design from a high level description thanks to CAD tools for architectural synthesis. However, this high level synthesis prevents front the use of some fast arithmetics unless a drastic increase of area. This paper discusses the introduction of such arithmetics in CAD tools and presents which problems it implies. As these problems are NP-complete, a solution based on ILP is proposed
Keywords :
circuit optimisation; high level synthesis; integer programming; linear programming; redundant number systems; CAD; ILP; NP-complete problem; area optimization; design; high-level synthesis; redundant arithmetic; Algorithm design and analysis; Arithmetic; Delay; Design automation; High level synthesis; Integer linear programming; Libraries; Pipelines; Resource management;
Conference_Titel :
ASIC, 1996., 2nd International Conference on
Conference_Location :
Shanghai
Print_ISBN :
7-5439-0940-5
DOI :
10.1109/ICASIC.1996.562756
