An augmented phase-leg configuration with shoot-through immunity and improvements for high-current operation

The augmented phase-leg configuration (APLC) features inherent immunity to shoot-through failures and a simplified gate drive circuit that eliminates the need for control dead time. This paper addresses several key design issues that must be resolved in order to successfully apply the APLC in applications with elevated current levels (>100A). The importance of minimizing key parasitic inductances is investigated, and the net reduction of the phase-leg efficiency caused by the series diode is found to be small (<1%) for bus voltages above 100 V_dc. An alternative APLC topology is presented using a synchronous rectifier MOSFET that offers reduced losses by decreasing the forward conduction drop of the series diode. A combination of analysis, simulation, and experimental tests is used to confirm the basic scalability of the APLC to current levels of 100 A or higher.