3W SPDT antenna switch design using standard 0.18¿m CMOS process

A high power SPDT antenna switch is designed and implemented using a standard 0.18 mum CMOS process. Multi-stack FETs structure with feed-forward capacitors in a Rx switch were chosen to achieve high power-handling capability of a Tx switch. Allowance of the negative voltage swing at either a source port or a drain port is ensured by applying the resistive body floating technique to the each switch device of multi-stack FETs. Intentional unequal division of the voltage swing level of the each NMOS device by the feed-forward capacitors helps the prevention of the channel formation of the OFF-state device. Experimental data shows that the proposed design achieves an 1 dB compression point of the input power at 34.5 dBm in 1.9 GHz. Also negative voltage supply at OFF state switch demonstrate further enhancement of power handling capability. The insertion loss of the Tx switch is 1.0 dB and 1.4 dB at 900 MHz and 1.9 GHz, respectively. The Rx switch has 1.4 dB and 1.8 dB insertion loss at 900 MHz and 1.9 GHz, respectively. Since the level of the power-handling capability achieved is close to the limitation of the device breakdown voltage, the reliability issue is studied in the case of both hard breakdown and soft breakdown.