VHDL description for SDH system simulation and circuit synthesis

Author

Dupont, O. ; Nancy, Th ; Wei, S.J. ; Leroy, J. ; Crappe, R.G.

Author_Institution

Lab. of Microelectron., Faculte Polytechnique de Mons, Belgium

fYear

1996

fDate

21-24 Oct 1996

Firstpage

93

Lastpage

95

Abstract

This paper presents a specific system architecture that was developed to define a set of circuits required to build a complete SDH (Synchronous Digital Hierarchy) system interfacing respectively with 2 Mbits/s, 34 Mbits/s and 139 Mbits/s PDH (Plesiochronous Digital Hierarchy) networks. The design methodology is based on high level description of complete SDH nodes in order to meet different objectives that could be defined at the project level. On one hand, the System Engineer has the capability to easily build models from precise specifications and execute functional simulation at the system level. On the other hand, the design engineer can adapt the VHDL code, eventually modify the partitioning and choose the circuits architecture in order to obtain the best hardware implementation

Keywords

hardware description languages; high level synthesis; synchronous digital hierarchy; 139 Mbit/s; 2 Mbit/s; 34 Mbit/s; SDH system simulation; VHDL; circuit synthesis; design; high level description; system architecture; Application specific integrated circuits; Bit rate; Central Processing Unit; Circuit simulation; Circuit synthesis; Containers; Laboratories; Microelectronics; Synchronous digital hierarchy; Virtual colonoscopy;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC, 1996., 2nd International Conference on

Conference_Location

Shanghai

Print_ISBN

7-5439-0940-5

Type

conf

DOI

10.1109/ICASIC.1996.562759

Filename

562759