• DocumentCode
    2947723
  • Title

    A high-throughput and low-complexity H.264/AVC intra 16×16 prediction architecture for HD video sequences

  • Author

    Orlandic, M. ; Svarstad, K.

  • Author_Institution
    Dept. of Electron. & Telecommun., Norwegian Univ. of Sci. & Technol., Trondheim, Norway
  • fYear
    2013
  • fDate
    26-28 Nov. 2013
  • Firstpage
    529
  • Lastpage
    532
  • Abstract
    Intra prediction reduces redundancy by exploiting the similarities between video samples within one video frame and it is characterized by high data dependency, high number of memory accesses and intensive computational complexity. This paper proposes a high-throughput and low-complexity intra 16×16 prediction architecture that supports H.264/AVC high profile. The high speed prediction for H.264 meets the requirement for real time encoding of HD sequences. The architecture is capable of processing all four prediction modes, including highly complex plane mode. Parallel processing of 16 pixels, corresponding to the 4×4 block, is employed. The design is able to encode entire macroblock within 48 cycles. The proposed architecture is synthesized and implemented on Kintex 705 - XC7K325T board and requires 94 MHz to encode 4k×2k at 60 fps in real time.
  • Keywords
    computational complexity; image sequences; parallel processing; video coding; HD video sequences; high data dependency; high-throughput low-complexity H.264-AVC intra 16×16 prediction; intensive computational complexity; macroblock; parallel processing; real time encoding; video samples; Clocks; Computer architecture; Encoding; Hardware; High definition video; Real-time systems; Video coding; FPGA; H.264/AVC; encoder; hardware implementation; intra prediction; plane mode;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Telecommunications Forum (TELFOR), 2013 21st
  • Conference_Location
    Belgrade
  • Print_ISBN
    978-1-4799-1419-7
  • Type

    conf

  • DOI
    10.1109/TELFOR.2013.6716283
  • Filename
    6716283