Title :
An I/Q channel 12-bit 200MS/s CMOS DAC with three stage decoders for wireless communication
Author :
Yu, Yunhua ; Shi, Haitao ; Ni, Weining
Author_Institution :
Sch. of Inf. & Control Eng., China Univ. of Pet. (East China), Dongying, China
Abstract :
This paper describes a 12-bit 200 MHz CMOS DAC for wireless communication. The proposed DAC consists of a unit current-cell matrix for 6 MSBs and a unit current-cell matrix for 4 NSBs and a binary-weighted array for 2 LSBs. In order to ensure the linearity of DAC, a double centro symmetric current matrix is designed by using the Q2 random walk strategy. A voltage limiter circuit that limits the switching voltage magnitude is designed to reduce the coupling effect from the control signal to the load and improve the dynamic performance.
Keywords :
CMOS integrated circuits; digital-analogue conversion; limiters; wireless channels; CMOS DAC; I/Q channel; binary weighted array; digital to analog converters; double centro symmetric current matrix; frequency 200 MHz; three stage decoders; unit current-cell matrix; voltage limiter circuit; wireless communication; word length 12 bit; CMOS analog integrated circuits; CMOS digital integrated circuits; Clocks; Decoding; Energy consumption; Linearity; Switches; Symmetric matrices; Wireless LAN; Wireless communication; CMOS mixed integrated circuit; DAC; Q2 Random Walk; current-steering;
Conference_Titel :
Wireless Communications & Signal Processing, 2009. WCSP 2009. International Conference on
Conference_Location :
Nanjing
Print_ISBN :
978-1-4244-4856-2
Electronic_ISBN :
978-1-4244-5668-0
DOI :
10.1109/WCSP.2009.5371403
