Top-down design for 32-bit RISC core

Author

Zhongyou, Xu ; Liu Honaxin ; Changsheng, Chou ; Xiaoli, Yang ; Lu, Dai ; Jingjing, Xu ; Li, Chi

Author_Institution

Northeast Microelectron. Inst., Shenyang, China

fYear

1996

fDate

21-24 Oct 1996

Firstpage

104

Lastpage

106

Abstract

This paper is to introduce the 32-bit RISC IU chip LC47811. It was designed and fabricated in China last year. It is designed as the core of embedded microcontrollers for future applications. The design of RISC chip started at RTL level with Top-Down methodology in June 1995, we generated the gate-level net-list by logic synthesis and complete the layout by automatic place and route on COMPASS in Sept. 1995. We finished all design, process, wafer test, bonding, packaging and final test in China by May 1996. This design is proved successful for the first time

Keywords

integrated circuit design; microcontrollers; reduced instruction set computing; 32 bit; COMPASS; IU chip; LC47811; RISC core; RTL level; automatic place and route; embedded microcontroller; gate-level net-list; layout; logic synthesis; top-down design; CMOS logic circuits; CMOS process; Large scale integration; Licenses; Logic design; Microelectronics; Reduced instruction set computing; Registers; Sun; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC, 1996., 2nd International Conference on

Conference_Location

Shanghai

Print_ISBN

7-5439-0940-5

Type

conf

DOI

10.1109/ICASIC.1996.562762

Filename

562762

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2948134