ProTest: a low cost rapid prototyping and test system for ASICs and FPGAs

Author

Jacomet, Marcel ; Walti, Roger ; Winzenried, Lukas ; Perez, Jaime ; Gysel, Martin

Author_Institution

Tech. Eng. School Biel, Switzerland

fYear

1997

fDate

21-23 Jul 1997

Firstpage

60

Lastpage

61

Abstract

The test bench methodology helps the design engineer to structure the simulation of his circuit. As showed in this paper, the test bench methodology can further be developed in, order to efficiently reuse simulation stimuli and response for the real device under test. As FPGAs are very often used to prototype an ASIC design, an easy switch between simulation and real hardware test is necessary to establish a rapid prototyping design and test environment. Our ProTest system closes the gap between the simulation and the test environment with a low cost and easy to use computer-aided-test environment

Keywords

VLSI; application specific integrated circuits; automatic testing; circuit CAD; design for testability; field programmable gate arrays; integrated circuit design; integrated circuit testing; logic CAD; logic testing; ASICs; FPGAs; ProTest; computer-aided-test environment; low cost rapid prototyping; test bench methodology; test system; Circuit simulation; Circuit testing; Computational modeling; Costs; Design engineering; Design methodology; Prototypes; Switches; System testing; Virtual prototyping;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronic Systems Education, 1997. MSE '97. Proceedings., 1997 IEEE International Conference on

Conference_Location

Arlington, VA

Print_ISBN

0-8186-7996-4

Type

conf

DOI

10.1109/MSE.1997.612547

Filename

612547