A novel pixel topology for on-the-fly programmable image processing

A novel pixel topology for real-time programmable image processing is presented. The circuit can implement a large class of spatio-temporal filters over a 3times3 pixels kernel. The image processing is based on two fundamental operations: absolute value of a difference and signal accumulation of partial results. On-the-fly processing approach is used to perform image filtering over high dynamic-range images. The pixel, designed in a CMOS 0.35 mum technology, has square shape with a side of 32.5 mum, consists of 30 transistors and presents a fill factor of 24%.