DocumentCode
2949672
Title
In-Network Snoop Ordering (INSO): Snoopy coherence on unordered interconnects
Author
Agarwal, Niket ; Peh, Li-Shiuan ; Jha, Niraj K.
Author_Institution
Dept. of Electr. Eng., Princeton Univ., Princeton, NJ
fYear
2009
fDate
14-18 Feb. 2009
Firstpage
67
Lastpage
78
Abstract
Realizing scalable cache coherence in the many-core era comes with a whole new set of constraints and opportunities. It is widely believed that multi-hop, unordered on-chip networks would be needed in many-core chip multiprocessors (CMPs) to provide scalable on-chip communication. However, providing ordering among coherence transactions on unordered interconnects is a challenge. Traditional approaches for tackling coherence either have to use ordered interconnects (snoop-based protocols) which lead to scalability problems, or rely on an ordering point (directory-based protocols) which adds indirection latency. In this paper, we propose In-Network Snoop Ordering (INSO), in which coherence requests from a snoop-based protocol are inserted into the interconnect fabric and the network orders the requests in a distributed manner, creating a global ordering among requests. Essentially, when coherence requests enter the network, they grab snoop-orders at the injection router before being broadcasted. A snoop-order specifies the global ordering of the particular request with respect to other requests. Before requests reach their destinations, they get ordered along the way, at intermediate routers and destination network interfaces. Our logical ordering scheme can be mapped onto any unordered interconnect. This enables a cache coherence protocol which exploits the low-latency nature of unordered interconnects without adding indirection to coherence transactions. Our full-system evaluations compare INSO against a directory protocol and a broadcast based Token Coherence protocol. INSO outperforms these protocols by up to 30% and 8.5%, respectively, on a wide range of scientific and emerging applications.
Keywords
cache storage; integrated circuit interconnections; microprocessor chips; broadcast based token coherence protocol; cache coherence protocol; coherence transactions; destination network interfaces; directory protocol; full-system evaluations; global ordering; in-network snoop ordering; intermediate routers; logical ordering scheme; many-core chip multiprocessors; multihop on-chip networks; scalable cache coherence; scalable on-chip communication; snoop-based protocol; unordered interconnects; unordered on-chip networks; Bandwidth; Broadcasting; Costs; Delay; Fabrics; Multicast protocols; Network interfaces; Network-on-a-chip; Scalability; Spread spectrum communication;
fLanguage
English
Publisher
ieee
Conference_Titel
High Performance Computer Architecture, 2009. HPCA 2009. IEEE 15th International Symposium on
Conference_Location
Raleigh, NC
ISSN
1530-0897
Print_ISBN
978-1-4244-2932-5
Type
conf
DOI
10.1109/HPCA.2009.4798238
Filename
4798238
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