• DocumentCode
    2949762
  • Title

    Versatile prediction and fast estimation of Architectural Vulnerability Factor from processor performance metrics

  • Author

    Duan, Lide ; Li, Bin ; Peng, Lu

  • Author_Institution
    Louisiana State Univ., Baton Rouge, LA
  • fYear
    2009
  • fDate
    14-18 Feb. 2009
  • Firstpage
    129
  • Lastpage
    140
  • Abstract
    The shrinking processor feature size, lower threshold voltage and increasing clock frequency make modern processors highly vulnerable to transient faults. Architectural vulnerability factor (AVF) reflects the possibility that a transient fault eventually causes a visible error in the program output, and it indicates a system´s susceptibility to transient faults. Therefore, the awareness of the AVF especially at early design stage is greatly helpful to achieve a trade-off between system performance and reliability. However, tracking the AVF during program execution is extremely costly, which makes accurate AVF prediction extraordinarily attractive to computer architects. In this paper, we propose to use boosted regression trees, a nonparametric tree-based predictive modeling scheme, to identify the correlation across workloads, execution phases and processor configurations between a key processor structure´s AVF and various performance metrics. The proposed method not only makes an accurate prediction but quantitatively illustrates individual performance variable´s importance to the AVF. Moreover, to reduce the prediction complexity, we also utilize a technique named patient rule induction method to extract some simple selecting rules on important metrics. Applying these rules during run time can fast identify execution intervals with a relatively high AVF.
  • Keywords
    microprocessor chips; regression analysis; trees (mathematics); architectural vulnerability factor; boosted regression tree; nonparametric tree-based predictive modeling; patient rule induction method; processor performance metrics; transient fault; Clocks; Frequency estimation; Hardware; Logic devices; Measurement; Predictive models; Regression tree analysis; State estimation; System performance; Testing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    High Performance Computer Architecture, 2009. HPCA 2009. IEEE 15th International Symposium on
  • Conference_Location
    Raleigh, NC
  • ISSN
    1530-0897
  • Print_ISBN
    978-1-4244-2932-5
  • Type

    conf

  • DOI
    10.1109/HPCA.2009.4798244
  • Filename
    4798244