Title :
Gate oxide protection in HV CMOS/DMOS integrated circuits: Design and experimental results
Author :
Chebli, R. ; Sawan, M. ; Savaria, Y.
Author_Institution :
Dept. of Electr. Eng., Ecole Polytech. de Montreal, Montreal, QC
Abstract :
This article presents a method for protecting the thin gate oxide of CMOS/HVDMOS transistor against damaging from high voltage signal applied to its gate. Also, it provides a design methodology and usage conditions related to this protection method. Based on this protection method, DC/DC up converter as well as level up shifter are proposed. The simulation and experimental results confirm the capability of the protection method and show its power to facilitate the design of high voltage circuits up to 300 V.
Keywords :
CMOS integrated circuits; DC-DC power convertors; HV CMOS-DMOS integrated circuits; gate oxide protection; level up shifter; thin gate oxide; Breakdown voltage; CMOS integrated circuits; Capacitors; Circuit simulation; Design methodology; EPROM; Nonvolatile memory; Protection; Signal design; Voltage control;
Conference_Titel :
Electronics, Circuits and Systems, 2005. ICECS 2005. 12th IEEE International Conference on
Conference_Location :
Gammarth
Print_ISBN :
978-9972-61-100-1
Electronic_ISBN :
978-9972-61-100-1
DOI :
10.1109/ICECS.2005.4633435
