HW/SW design and realization of a size-reconfigurable DCT accelerator

Author

Obeid, Abdulfattah ; Murgan, Tudor ; Taadou, Abdelouahid ; Glesner, Manfred

Author_Institution

Inst. for Microelectron. Syst., Darmstadt Univ. of Technol., Darmstadt

fYear

2005

fDate

11-14 Dec. 2005

Firstpage

1

Lastpage

4

Abstract

In this paper a reconfigurable size MDCT accelerator is modeled and synthesized. Starting from the C code of the desired application that cannot run in real time on the given platform (a LEON processor) we isolate the computationally extensive modules of the MDCT to be implemented an accelerator. Because of similarities of their data flow graphs we modify the R2SDF architecture of the FFT and fit it to the MDCT algorithm by adding modules to solve the irregularities in its data flow graphs. The resultant architecture is modular and size-reconfigurable.

Keywords

data flow graphs; digital signal processing chips; discrete cosine transforms; fast Fourier transforms; hardware-software codesign; logic design; FFT; HW/SW design; MDCT algorithm; R2SDF architecture; data flow graph; digital signal processing system; discrete cosine tranform accelerator; hardware-software design; size-reconfigurable DCT accelerator; Acceleration; Application specific integrated circuits; Computer architecture; Decoding; Digital signal processing; Discrete cosine transforms; Flow graphs; Hardware; Open source software; Real time systems;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 2005. ICECS 2005. 12th IEEE International Conference on

Conference_Location

Gammarth

Print_ISBN

978-9972-61-100-1

Electronic_ISBN

978-9972-61-100-1

Type

conf

DOI

10.1109/ICECS.2005.4633437

Filename

4633437