Design and hardware implementation of digital channel selection decimating filter for multistandard receiver

This paper presents a low-power design and an area-efficient FPGA implementation of digital channel selection decimating filter for multistandard receiver. Authors propose an optimized multistage decimation filter for a front-end composed by an Homodyne wide-band RF receiver and sigma-delta modulator. Design flow of hardware architecture is presented through the choice of filter structure and architecture. Several results are given to evaluate performances and complexity of designed FPGA-based implementation that can support GSM, DECT and UMTS standard.