Title :
HEC identifying in SDH-ATM interface circuit
Author :
Zhi, Jun ; Wei, Shaojun ; Chen, Hongyi
Author_Institution :
Inst. of Microelectron., Tsinghua Univ., Beijing, China
Abstract :
While transmitting the ATM (asynchronous transfer mode) cells using the SDH (synchronous digital hierarchy)-based physical layer, we have to identify the cell boundaries. Either using the H4 byte of the VC4-POH (virtual container 4-path overhead) or HEC (header error control) byte checking method can be used. In this paper, two circuit architectures based on 0.8 μm CMOS technique are presented using HEC method to identify the ATM cell boundaries
Keywords :
B-ISDN; CMOS digital integrated circuits; asynchronous transfer mode; error correction; synchronous digital hierarchy; 0.8 micron; CMOS technique; H4 byte; HEC; SDH-ATM interface circuit; VC4-POH; asynchronous transfer mode; byte checking method; cell boundaries; circuit architectures; header error control; synchronous digital hierarchy; virtual container 4-path overhead; Asynchronous transfer mode; Circuits; Clocks; Containers; Error correction; Microelectronics; Physical layer; Polynomials; Shift registers; Synchronous digital hierarchy;
Conference_Titel :
ASIC, 1996., 2nd International Conference on
Conference_Location :
Shanghai
Print_ISBN :
7-5439-0940-5
DOI :
10.1109/ICASIC.1996.562775
