Bus Regrouping method to Optimize Power in DSM Technology

In many digital processors, the power dissipation in the bus is a major part of the total chip power dissipation. For CMOS circuits most power is dissipated as a dynamic power for charging and discharging node capacitances. In non deep sub-micron technology, these capacitances are mainly the substrate capacitances of the bus wires where as in deep sub-micron technology inter wire capacitance also contribute to total capacitance. The main objective of this paper is to explain a new algorithm called Bus Regrouping Method to reduce coupling transitions. As a consequence the power dissipation due to the coupling capacitance or inter wire capacitance in deep sub-micron technology is optimized.