A Novel Scaling Theory for Effective Conductive Path Effect of Double Gate (DG) MOSFETs for Nano-Scale CMOS Circuit Design

The steady down-scaling of complementary metal oxide semiconductor (CMOS) device dimensions has been the main stimulus to the growth of microelectronics and computer-aided ultra large scale integration (ULSI) design. Double gate (DG) SOI MOSFET is one of the most promising technologies for ultimate scaling of CMOS technology. By studying the subthreshold conducting phenomenon of DG MOSFETs, the effective conductive path effect (ECPE) is employed to acquire the natural length to guide the design. With ECPE, the minimum channel potential is used to monitor the subthreshold behavior. The effect of ECPE on scaling factor significantly improved the subthreshold swing compared to conventional scaling rule. The accuracy of results obtained using our analytical model is verified using 2-D numerical simulation. The model offers the basic designing guidance for double-gate MOSFETs.