Design of ultra low-power analog cells with dynamic current biasing

This paper describes design strategies for ultra low-power analog cells. It is assumed that the circuits are used in sampled-data systems with only capacitors and switches. The operation requires large currents to quickly charging or discharging capacitors and, after a transient, a very small quiescent current. The proposed strategy uses dynamically controlled bias current that leads to a very low average power consumption while the slew-rate and frequency response is good enough. Two categories of circuits are discussed: low-voltage OTA and comparators. For both circuits simulation results confirm the validity of the basic idea and show good performances with average currents in the sub micro-ampere range.