A chip architecture for 2.048 Mbits/s PDH/SDH mapping/desynchronisation

Author

Wei, Shaojun ; Dupont, Olivier ; Nancy, Thierry ; Leroy, Jacques ; Crappe, Raymond ; Xu, Li

Author_Institution

IMETU, Tsinghua Univ., Beijing, China

fYear

1996

fDate

21-24 Oct 1996

Firstpage

163

Lastpage

166

Abstract

In this paper, a chip architecture for PDH/SDH multiplexing/demultiplexing is presented, including mapping/desynchronisation and the 1+1 protection transmission/reception. The one-step mapping scheme is used to insert/extract 21 tributary units of 2.048 Mbits/s directly into/from STM-1 frame. The time slot a VC-12 occupies in C-4 can be programmed by an external CPU. Programmable control mechanism allows the user to have a leaking period up to 34952 multi-frames and an error of 0.0167UI only at low end desynchronisation output

Keywords

CMOS digital integrated circuits; demultiplexing equipment; multiplexing equipment; pipeline processing; synchronous digital hierarchy; transceivers; 1+1 protection transmission/reception; 2.048 Mbit/s; PDH/SDH mapping/desynchronisation; STM-1 frame; VC-12; chip architecture; leaking period; multiplexing/demultiplexing; one-step mapping scheme; programmable control mechanism; time slot; tributary units; Containers; Error correction; Jitter; Laboratories; Microelectronics; Programmable control; Protection; Road transportation; Signal mapping; Synchronous digital hierarchy;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC, 1996., 2nd International Conference on

Conference_Location

Shanghai

Print_ISBN

7-5439-0940-5

Type

conf

DOI

10.1109/ICASIC.1996.562777

Filename

562777