Title :
Estimation of control logic for binary synthesis
Author :
Sangeetha, M. ; Perinbam, J.R.P. ; Kumaran, M.
Author_Institution :
Anna Univ., Guindy
Abstract :
The behavioral description is transformed into binary level representation. The assembly instructions are profiled by providing test vectors. The critical kernel of the profiled data is identified manually and partitioned into hardware. The partitioned software module is transformed into control data flow graph. The control logic of the control data flow graph for the software module partitioned to hardware can be estimated using behavioral network graph.
Keywords :
data flow graphs; hardware-software codesign; instruction sets; logic partitioning; CAD tool; assembly instructions; binary level representation; binary synthesis; control data flow graph; control logic estimation; partitioned software module; test vectors; Assembly; Educational institutions; Embedded system; Flow graphs; Hardware; Kernel; Logic; Optimizing compilers; Software performance; Testing;
Conference_Titel :
Signal Processing, Communications and Networking, 2008. ICSCN '08. International Conference on
Conference_Location :
Chennai
Print_ISBN :
978-1-4244-1924-1
Electronic_ISBN :
978-1-4244-1924-1
DOI :
10.1109/ICSCN.2008.4447237
