Embedded software implementation of an adaptive baseband predistorter

This paper is intended to present an adaptive digital baseband predistortion (DPD) method for power amplifier linearization using an hybrid DSP/FPGA based architecture. The DPD reference scheme is designed around two processing stages. The first of them is the real time fast loop based on a Look Up Table (LUT) and performed by a Field Programmable Gate Array (FPGA). The second stage, being at the center of interest of this article, is the adaptive loop designed as embedded and reconfigurable software in a Digital Signal Processor (DSP).