Title :
New architectures for modulo 2N - 1 adders
Author :
Dimitrakopoulos, G. ; Nikolos, D.G. ; Vergos, H.T. ; Nikolos, D. ; Efstathiou, C.
Author_Institution :
Inf. Dept., Univ. of Patras, Patras
Abstract :
Two architectures for parallel-prefix modulo 2n - 1 adders are presented in this paper. For large wordlengths we introduce the sparse modulo 2n - 1 adders that achieve significant reduction of the wiring complexity without imposing any delay penalty. Then, the Ling-carry formulation of modulo 2n - 1 addition is presented. Ling modulo adders save one logic level of implementation and provide high-speed solutions for smaller adder widths, where wiring complexity is small. The performance of the proposed adders has been validated with static CMOS implementations. In all examined cases, the proposed designs achieve significant savings in both area and delay compared to previously published architectures.
Keywords :
CMOS logic circuits; adders; logic design; CMOS; Ling-carry formulation; delay penalty; modulo 2N-1 adder; parallel-prefix adder; wiring complexity; Adders; CMOS logic circuits; Computer architecture; Computer networks; Concurrent computing; Delay; Informatics; Routing; Signal generators; Wiring;
Conference_Titel :
Electronics, Circuits and Systems, 2005. ICECS 2005. 12th IEEE International Conference on
Conference_Location :
Gammarth
Print_ISBN :
978-9972-61-100-1
Electronic_ISBN :
978-9972-61-100-1
DOI :
10.1109/ICECS.2005.4633502
