An embedded IDDQ testing circuit and technique

Quiescent current (I_DDQ) testing is a valuable defect detection technique in CMOS ICs. However, its application in very deep submicron technologies is susceptible to the increased transistor leakage current. In this paper, an I_DDQ testing technique and circuit are presented based on the background current compensation concept. This technique is independent from process and temperature variations and first experimental results from a fabricated circuit show that it is able to extend the viability of I_DDQ testing in future nanometer technologies.