DocumentCode
2951462
Title
CMOS pipelined ADC employing dither to improve linearity
Author
Fetterman, H. Scott ; Martin, David G. ; Rich, David A.
Author_Institution
Lucent Technol., AT&T Bell Labs., Allentown, PA, USA
fYear
1999
fDate
1999
Firstpage
109
Lastpage
112
Abstract
This paper presents a new method for applying linearity improving dither to a pipelined ADC employing digital error correction. This dither energy remains internal to the converter, only causing correctable errors in the internal uncorrected digital data stream. Unlike adding dither to the input signal, this new dither method does not consume signal bandwidth or dynamic range. Spurious free dynamic range improvements of 15 dB have been realized
Keywords
CMOS integrated circuits; analogue-digital conversion; error correction; pipeline processing; CMOS pipelined ADC; digital error correction; dither; dynamic range improvement; linearity improvement; Analog-digital conversion; Bandwidth; Dynamic range; Error correction; Linearity; Noise reduction; Pipelines; Sampling methods; Signal to noise ratio; Software radio;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits, 1999. Proceedings of the IEEE 1999
Conference_Location
San Diego, CA
Print_ISBN
0-7803-5443-5
Type
conf
DOI
10.1109/CICC.1999.777253
Filename
777253
Link To Document