Title :
3D integration of high mobility InGaAs nFETs and Ge pFETs for ultra low power and high performance CMOS
Author :
Irisawa, T. ; Oda, Masaomi ; Kamimuta, Y. ; Moriyama, Y. ; Ikeda, Ken-ichi ; Mieda, E. ; Jevasuwan, W. ; Maeda, T. ; Ichikawa, Osamu ; Osada, Takenori ; Hata, Masaharu ; Tezuka, Taro
Author_Institution :
Collaborative Res. Team Green Nanoelectron. Center (GNC), AIST, Tsukuba, Japan
Abstract :
InGaAs/Ge stacked 3D CMOS inverters have been successfully demonstrated down to Vdd = 0.2 V. The negligible degradation of the top and the bottom device characteristics indicates high technical feasibility of the InGaAs/Ge stacked 3D integration for ultra low-power and high performance CMOS.
Keywords :
CMOS logic circuits; III-V semiconductors; MOSFET; elemental semiconductors; gallium arsenide; germanium; indium compounds; logic gates; low-power electronics; three-dimensional integrated circuits; 3D integration scheme; InGaAs-Ge; device characteristics; high mobility nFETs; high performance CMOS; pFETs; stacked 3D CMOS inverters; ultralow power CMOS; voltage 0.2 V; CMOS integrated circuits; Fabrication; Indium gallium arsenide; Logic gates; MOSFET; MOSFET circuits; Three-dimensional displays;
Conference_Titel :
SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2013 IEEE
Conference_Location :
Monterey, CA
DOI :
10.1109/S3S.2013.6716513
