A bandpass sigma-delta modulator IC with digital branch-mismatch correction

Author

Comino, Vittorio ; Lu, A.C.

Author_Institution

Wireless Technol. Res., Lucent Technol., Holmdel, NJ, USA

fYear

1999

fDate

1999

Firstpage

129

Lastpage

132

Abstract

A bandpass sigma delta modulator, integrated in a 0.35 μm CMOS technology, samples a 82 MHz signal with a 109 MHz clock. The resolution is 11 bits over a 200 kHz bandwidth. To reach higher sampling rates the integrated circuit sub-samples the signal and uses the conventional two-branch parallel structure. A novel digital correction technique reduces the mismatch between the parallel branches increasing the signal to image ratio by 10 to 15 dB. This technique can be extended to structures with higher levels of parallelism

Keywords

CMOS integrated circuits; calibration; parallel processing; radio receivers; sigma-delta modulation; signal sampling; 0.35 micron; 109 MHz; 200 kHz; 82 MHz; A/D conversion; ADC; CMOS technology; bandpass sigma-delta modulator IC; digital branch-mismatch correction; digital correction technique; sampling rates; signal subsampling; two-branch parallel structure; wireless receiver; Bandwidth; CMOS technology; Clocks; Delta modulation; Delta-sigma modulation; Digital integrated circuits; Digital modulation; Image sampling; Integrated circuit technology; Signal resolution;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits, 1999. Proceedings of the IEEE 1999

Conference_Location

San Diego, CA

Print_ISBN

0-7803-5443-5

Type

conf

DOI

10.1109/CICC.1999.777258

Filename

777258