Title :
Low Latency VLSI Architecture for the Radix-4 CORDIC Algorithm
Author :
Lakshmi, B. ; Dhar, A.S.
Author_Institution :
Dept. of Electron. & Electr. Commun. Eng., Indian Inst. of Technol. Kharagpur, Kharagpur
Abstract :
The current trend of hardware intensive signal processing is based on the CORDIC. Over the years many architectures have been proposed to address issues pertaining to throughput and latency. In this paper, we are proposing a pipelined architecture for the VLSI implementation of radix-4 CORDIC rotator with redundant arithmetic to achieve low latency compared to the available architectures.
Keywords :
VLSI; digital arithmetic; signal processing; VLSI architecture; hardware intensive signal processing; radix-4 CORDIC algorithm; Arithmetic; Computer architecture; Delay; Hardware; Iterative algorithms; Region 10; Sections; Signal processing algorithms; Throughput; Very large scale integration; CORDIC algorithm; radix-4; redundant arithmetic; rotation mode;
Conference_Titel :
Industrial and Information Systems, 2008. ICIIS 2008. IEEE Region 10 and the Third international Conference on
Conference_Location :
Kharagpur
Print_ISBN :
978-1-4244-2806-9
Electronic_ISBN :
978-1-4244-2806-9
DOI :
10.1109/ICIINFS.2008.4798377
