A 4.9 ns, 3.3 volt, 512 macrocell, CMOS PLD with hot socket protection and fast in system programming

Author

Vest, Brad ; Liang, Gwen ; Chan, Mark ; Chun, Eric ; Fiester, Mark ; Ding, Weiying ; Lau, Edmond ; Lin, Guu ; Nouban, Behzad ; Reese, Dirk ; Smith, Mian ; Tran, Nghia ; Wong, Stephanie ; Woo, Michael ; Wong, Myron ; Costello, John

Author_Institution

ALTERA Corp., San Jose, CA, USA

fYear

1999

fDate

1999

Firstpage

187

Lastpage

190

Abstract

A high density, Programmable Logic Device (PLD) family developed for hot socketing and high performance is discussed. The family is fabricated on a 0.32 um quadruple layer metal process. The largest family member is a 512 macrocell part with typical pin to pin delays of 4.9 ns. The design techniques and testing methodology to guarantee safe hot socketing are described. Streamlined In System Programming (ISP) and circuits used to configure EEPROM cells with a 3.3-V supply are also discussed

Keywords

CMOS logic circuits; integrated circuit design; integrated circuit testing; network routing; programmable logic devices; protection; 0.32 mum; 3.3 V; 4.9 ns; CMOS PLD; charge sharing; hot socket protection; leakage curents; programming time; quadruple layer metal process; safe hot socketing; speed; system programming; Delay; EPROM; Logic programming; Macrocell networks; Pins; Power system protection; Printed circuits; Programmable logic devices; Sockets; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits, 1999. Proceedings of the IEEE 1999

Conference_Location

San Diego, CA

Print_ISBN

0-7803-5443-5

Type

conf

DOI

10.1109/CICC.1999.777271

Filename

777271