Flexible reconfigurable multiplier blocks suitable for enhancing the architecture of FPGAs

Author

Haynes, Simon D. ; Ferrari, Antonio B. ; Cheung, Peter Y K

Author_Institution

Dept. of Electr. & Electron. Eng., Imperial Coll. of Sci., Technol. & Med., London, UK

fYear

1999

fDate

1999

Firstpage

191

Lastpage

194

Abstract

A new architecture is proposed for configurable blocks which can be used to dynamically construct multipliers. An array of these blocks is capable of being configured to perform any 8m by 8n bits signed/unsigned binary multiplication. The new design is based on the radix-4 overlapped multiple-bit scanning algorithm. This yields excellent multiplication times, at the same time allowing multiply accumulate (MAC) operations, without modification. The new design is compared to our previous scheme, and shown to be both faster and require fewer transistors

Keywords

VLSI; field programmable gate arrays; integrated circuit design; logic CAD; multiplying circuits; FPGA; architecture; flexible reconfigurable multiplier blocks; multiplication times; multiply accumulate operations; radix-4 overlapped multiple-bit scanning algorithm; Adders; Algorithm design and analysis; Arithmetic; Array signal processing; Educational institutions; Field programmable gate arrays; Graphics; Manufacturing; Signal processing algorithms; Telecommunications;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits, 1999. Proceedings of the IEEE 1999

Conference_Location

San Diego, CA

Print_ISBN

0-7803-5443-5

Type

conf

DOI

10.1109/CICC.1999.777272

Filename

777272