DocumentCode
2951866
Title
Digital correlator EPLD design
Author
Jianzhong, Chen ; Yonggui, Li ; Minzhi, Zhou ; Fuqiang, Yao
Author_Institution
Res. Inst., PLA, Nanjing, China
fYear
1996
fDate
21-24 Oct 1996
Firstpage
183
Lastpage
186
Abstract
This paper begins with the imperativeness of applying EPLD technique to digital correlator design of communication systems. On this basis, it explains the relative technical problems existing in the EPLD design of a digital correlator, analyses the hardware resource provided by EPLD and gives a description of an example of design as well as relevant test results. It concludes with several suggestions for the expansion of EPLD functions
Keywords
application specific integrated circuits; correlators; digital signal processing chips; logic design; programmable logic devices; DSP chip; EPLD design; digital correlator design; hardware resource; Correlators; Energy consumption; Hardware; Logic arrays; Maintenance; Microprocessors; Power system reliability; Privacy; Programmable logic arrays; System testing;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC, 1996., 2nd International Conference on
Conference_Location
Shanghai
Print_ISBN
7-5439-0940-5
Type
conf
DOI
10.1109/ICASIC.1996.562782
Filename
562782
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