DocumentCode
2951967
Title
FPGA Parallel Implementation of CMAC Type Neural Network with on Chip Learning
Author
Brassai, S.T. ; Bakó, L. ; Dan, S.
Author_Institution
Fac. of Tech. & Human Sci., Sapientia Hungarian Univ. of Transilvania, Targu-Mures
fYear
2007
fDate
Yearly 17 2007-May 18 2007
Firstpage
111
Lastpage
115
Abstract
The hardware implementation of neural networks is a new step in the evolution and use of neural networks in practical applications. The CMAC cerebellar model articulation controller is intended especially for hardware implementation, and this type of network is used successfully in the areas of robotics and control, where the real time capabilities of the network are of particular importance. The implementation of neural networks on FPGA´s has several benefits, with emphasis on parallelism and the real time capabilities. This paper discusses the hardware implementation of the CMAC type neural network, the architecture and parameters and the functional modules of the hardware implemented neuro-processor.
Keywords
cerebellar model arithmetic computers; field programmable gate arrays; neural chips; parallel processing; cerebellar model articulation controller; field programmable gate array; functional module architecture; on chip learning; parallel CMAC type neural network implementation; Biological system modeling; Field programmable gate arrays; Input variables; Multilayer perceptrons; Network-on-a-chip; Neural network hardware; Neural networks; Nonlinear dynamical systems; Quantization; Vectors; CMAC; FPGA; neural networks; neural networks hardware implementation;
fLanguage
English
Publisher
ieee
Conference_Titel
Applied Computational Intelligence and Informatics, 2007. SACI '07. 4th International Symposium on
Conference_Location
Timisoara
Print_ISBN
1-4244-1234-X
Type
conf
DOI
10.1109/SACI.2007.375494
Filename
4262496
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