Lowpower design of multipliers using a full-adder isolation technique

In this paper a new technique for the design of combinational circuits for low power is introduced. According to this technique, we bypass blocks of logic when their function is not required, using low delay and area overhead components (transmission gates). The internal state of these blocks is kept unchanged, so the switching activity of the circuit is minimized, resulting to low power consumption. The proposed idea is applied in the design of a carry-save array multiplier with significant power saving.