Title :
A 1.8 V, 2.0 ns cycle, 32 KB embedded memory with interleaved castout/reload
Author :
Sullivan, Steven ; Johnson, Brad ; Reid, Douglas ; Taylor, Scott
Author_Institution :
Motorola Somerset Design Center, Austin, TX, USA
Abstract :
This paper describes the key circuit features of the 32 KB data cache memory embedded in the first AltiVecTM enhanced PowerPC TM microprocessor. The memory array implements a castout/reload scheme that allows both a read and a write operation within a single machine cycle which greatly increases cache bandwidth. A newly implemented vector alignment multiplexer supports the additional vector instructions. The design incorporates self-resetting and dynamic circuit techniques to achieve a cycle time of less than 2.0 ns fabricated in a 1.8-volt, 0.2 μm, 6-layer copper CMOS process
Keywords :
CMOS memory circuits; cache storage; microprocessor chips; multiplexing equipment; 0.2 micron; 1.8 V; 2.0 ns; 32 KB; AltiVec enhanced PowerPC microprocessor; CMOS process; cache bandwidth; cycle time; data cache memory; dynamic circuit techniques; embedded memory; interleaved castout/reload; machine cycle; self-resetting techniques; vector alignment multiplexer; vector instructions; Aluminum; Cache memory; Capacitance; Copper; Delay; Fuses; Integrated circuit interconnections; Logic arrays; Multiplexing; Voltage;
Conference_Titel :
Custom Integrated Circuits, 1999. Proceedings of the IEEE 1999
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-5443-5
DOI :
10.1109/CICC.1999.777281
