Synthesis and comparison of low-power high-throughput architectures for SAD calculation

This paper presents the standard-cells synthesis and comparison of parallel hardware architectures for the Sum of Absolute Differences (SAD) datapath, focusing on different design points such as high-performance (maximum throughput) and the tradeoff between high-performance and low-power dissipation (isoperformance target). Clock gating and different combination of parallelism and pipeline architectural techniques were explored in this work. In order to generate the results, we used the TSMC 0.18 μm standard-cells library with standard, slow and fast cells, and the back-end Cadence tools, e.g. Power Analysis, for the power measurements. We achieved significant power reduction for the architectures with low-frequency and high parallelism, slow cells and mainly with only one pipeline stage.