A novel architecture for CABAC decoding (H.264/AVC)

The ITU-T H.264/MPEG-4 Part 10 Advanced Video Coding standard provides a reduction up to 50% of the bitstream rate if compared to previous standards. Among the innovation presented we should highlight the CABAC entropy coding (Context-based Adaptive Binary Arithmetic Coding), which shows a reduction of 9% to 14% in the bit-stream rate, when compared to the CAVLC basic entropy coding. The strictly sequential nature of the algorithm introduces challenges for its efficient implementation, which requires dedicated hardware to achieve real time for high definition profiles. This paper proposes a new architecture for a dedicated hardware implementation of CABAC decoding with optimized performance, aiming to support the H264/AVC 1080p video decoding, according to the Main and High profiles, in real time. The architecture was prototyped in FPGA, reaching 75 MHz and decoding performance ranging from 20 to 33 Mbins/s.