DocumentCode
2952077
Title
PAC DSP Core and Application Processors
Author
Chang, David Chih-Wei ; Liao, I-Tao ; Lee, Jenq-Kuen ; Chen, Wen-Feng ; Tseng, Shau-Yin ; Jen, Chein-Wei
Author_Institution
SoC Technol. Center, Ind. Technol. Res. Inst., Hsinchu
fYear
2006
fDate
9-12 July 2006
Firstpage
289
Lastpage
292
Abstract
This paper provides an overview of the parallel architecture core (PAC) project led by SoC Technology Center of Industrial Technology Research Institute (STC/ITRI) in Taiwan. The background of PAC project, a brief introduction to PAC core technologies, PAC SoC development suite, PAC benchmarks, and applications are presented. The main objective of the PAC development plan is to enhance industrial development competitiveness in the core technology related to key components, especially for portable multimedia applications
Keywords
digital signal processing chips; parallel architectures; system-on-chip; DSP core; PAC; SoC development; application processor; benchmark; industrial development; parallel architecture core project; portable multimedia application; Assembly; Consumer electronics; Digital signal processing; Digital signal processing chips; Energy consumption; Energy management; Kernel; Multimedia systems; Programming; VLIW;
fLanguage
English
Publisher
ieee
Conference_Titel
Multimedia and Expo, 2006 IEEE International Conference on
Conference_Location
Toronto, Ont.
Print_ISBN
1-4244-0366-7
Electronic_ISBN
1-4244-0367-7
Type
conf
DOI
10.1109/ICME.2006.262455
Filename
4036593
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