Clock and data recovery for 1.25 Gb/s Ethernet transceiver in 0.35 μm CMOS

Author

Iravani, Kamran ; Saleh, Farid ; Lee, Donald ; Fung, Patrick ; Ta, Paul ; Miller, Gary

Author_Institution

VLSI Technol. Inc., San Jose, CA, USA

fYear

1999

fDate

1999

Firstpage

261

Lastpage

264

Abstract

A Clock/Data recovery (CDR) PLL with a VCO running at half the rate for gigabit serial data communication is described. A Novel feedback biasing circuit technique is used between the VCO and the charge pump to minimize any systematic phase offset error due to process and temperature variations. The receiver gain is boosted at high frequencies to compensate for the loss introduced by the cable. Improved CML logic is used to broadband the signal path. The CDR core consumes 150 mW at 3.3 V in 0.35 μm CMOS, and has a Bit-Error Rate (BER) of 10 ^-14 for the input jitter of 500 ps

Keywords

CMOS integrated circuits; circuit feedback; current-mode logic; data communication equipment; digital communication; error statistics; high-speed integrated circuits; local area networks; mixed analogue-digital integrated circuits; synchronisation; transceivers; 0.35 micron; 1.25 Gbit/s; 150 mW; 3.3 V; ASIC; BER; CML logic; Ethernet transceiver; VCO; bit-error rate; cable loss; charge pump; clock/data recovery PLL; feedback biasing circuit technique; gigabit serial data communication; phase offset error; process variations; receiver gain; temperature variations; Bit error rate; Charge pumps; Clocks; Data communication; Ethernet networks; Feedback circuits; Phase locked loops; Temperature; Transceivers; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits, 1999. Proceedings of the IEEE 1999

Conference_Location

San Diego, CA

Print_ISBN

0-7803-5443-5

Type

conf

DOI

10.1109/CICC.1999.777287

Filename

777287