Analog to digital converter for binary and multiple-valued logic

This paper presents a parallel architecture for an N-digit and B multiple-valued logic analog to digital converter (B-MVL-ADC), where B stands for the number of levels of the multiple-valued logic. The B-MVL-ADC is based on the modulo (MOD) operator and is built by making N replicas of 1-digit converter. Simulations and discrete implementation results, for the binary ADC (2-MVL-ADC) and for the 3-MVL-ADC architecture, illustrate circuit feasibility and correct functionality, which demonstrate architectural properties such as scalability and linear complexity when the base of the digital representation is B=2^m, m=1,2,...