Analog to digital converter for binary and multiple-valued logic

Author

Romero, Milton E R ; Martins, Evandro M. ; Santos, Ricardo R. ; Gonz, Mario E D

Author_Institution

Fed. Univ. of Mato Grosso do Sul, Campo Grande, Brazil

fYear

2011

fDate

23-25 Feb. 2011

Firstpage

1

Lastpage

4

Abstract

This paper presents a parallel architecture for an N-digit and B multiple-valued logic analog to digital converter (B-MVL-ADC), where B stands for the number of levels of the multiple-valued logic. The B-MVL-ADC is based on the modulo (MOD) operator and is built by making N replicas of 1-digit converter. Simulations and discrete implementation results, for the binary ADC (2-MVL-ADC) and for the 3-MVL-ADC architecture, illustrate circuit feasibility and correct functionality, which demonstrate architectural properties such as scalability and linear complexity when the base of the digital representation is B=2^m, m=1,2,...

Keywords

analogue-digital conversion; multivalued logic; analog to digital converter; binary-valued logic; digital representation; linear complexity; modulo operator; multiple-valued logic; parallel architecture; Architecture; Complexity theory; Computer architecture; Converters; Integrated circuit modeling; Radiation detectors; Voltage control; Analog to digital converter; Binary logic; Multiple-valued logic;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (LASCAS), 2011 IEEE Second Latin American Symposium on

Conference_Location

Bogata

Print_ISBN

978-1-4244-9484-2

Type

conf

DOI

10.1109/LASCAS.2011.5750283

Filename

5750283