Behavioral model of charge pumps with VHDL

A behavioral model of an N-stages charge pump is here presented. The description language used to develop the model is the VHDL thus permitting simulations of both digital and analog systems, such as nonvolatile memories. Moreover, the presented model allows a huge reduction in the simulation time also maintaining a good agreement with transistor level simulations. For a useful comparison, a three stages charge pump was simulated with Symphony EDA Sonata (event-driven VHDL simulator) and Spectre (transistor level simulator). The obtained result confirmed the validity of the developed description in terms of accuracy and low required simulation´s time.