Title :
A 62.5-250 MHz multi-phase delay-locked loop using a replica delay line with triply controlled delay cells
Author :
Moon, Yongsam ; Choi, Jongsang ; Lee, K. Yeongho ; Jeong, Deog-Kyoon ; Kim, Min-Kyu
Author_Institution :
Seoul Nat. Univ., South Korea
Abstract :
This paper describes a low-jitter multi-phase delay-locked loop (DLL) with a wide operating range of 62.5-250 MHz. A replica delay line attached to the core DLL enables it to fully utilize the frequency range of its voltage-controlled delay line. The DLL incorporates dynamic phase detectors and triply controlled delay cells with duty-cycle correction capability to generate equally spaced eight-phase clocks. The chip is fabricated using a 0.35 μm CMOS process. The measured jitter is suppressed to be less than 44 ps peak-to-peak over the operating frequency range in a noisy environment with other digital circuits activated on the same chip
Keywords :
CMOS integrated circuits; delay lines; delay lock loops; integrated circuit noise; mixed analogue-digital integrated circuits; phase detectors; 0.35 micron; 62.5 to 250 MHz; CMOS process; duty-cycle correction capability; dynamic phase detectors; frequency range; multi-phase delay-locked loop; noisy environment; operating frequency range; operating range; replica delay line; triply controlled delay cells; voltage-controlled delay line; CMOS process; Circuit noise; Clocks; Delay lines; Detectors; Frequency measurement; Jitter; Phase detection; Semiconductor device measurement; Voltage;
Conference_Titel :
Custom Integrated Circuits, 1999. Proceedings of the IEEE 1999
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-5443-5
DOI :
10.1109/CICC.1999.777295
