Title :
A ±25 ps jitter 1.9 V CMOS PLL for UltraSPARC microprocessor
Author_Institution :
Sun Microsyst., Palo Alto, CA, USA
Abstract :
A PLL with a power supply voltage referenced loop filter for UltraSPARC microprocessor clock generation has measured ±25 ps cycle-to-cycle jitter at 1.9 V and 360 MHz. The operating frequency range is from 8.5 MHz to 660 MHz and lowest power supply is 1.35 v at 400 MHz. The power supply noise rejection of 1.3 ps/50 mv is achieved. The measured cycle-to-cycle jitter for 400 mVpp sinusoidal AC signal at power supply of 1.9 V is ±37 ps
Keywords :
CMOS analogue integrated circuits; integrated circuit design; low-power electronics; phase locked loops; timing jitter; 1.35 to 1.9 V; 8.5 to 660 MHz; CMOS PLL; UltraSPARC microprocessor; clock generation; cycle-to-cycle jitter; operating frequency range; power supply noise rejection; power supply voltage referenced loop filter; Clocks; Filters; Frequency; Jitter; Microprocessors; Phase locked loops; Power generation; Power measurement; Power supplies; Voltage;
Conference_Titel :
Custom Integrated Circuits, 1999. Proceedings of the IEEE 1999
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-5443-5
DOI :
10.1109/CICC.1999.777296
