On the design of low noise and power efficient onchip oscillators

A design technique for a low noise low power LC-VCO is presented. By considering the thermal noise generated by the switching transistors, the resonator and the biasing circuit, we derived a complete phase noise expression for the 1/f² region. We observed that this expression is compatible with a geometric programming formulation of the VCO. Thus, an optimal device geometry for the VCO-core and its polarization circuit is simultaneously obtained for minimum power consumption under several different design specifications, including phase noise, oscillation frequency, tuning range, oscillation amplitude, loop gain and inductor geometry. Additionally, through the generation of optimal trade-off curves, some remarkable considerations about the impact of design specifications on the power consumption are reviewed. As a design example, a low power LC-VCO for the 2.45GHz ISM band, with phase noise of -130 dBc/Hz@3MHz and FOM of 180dB, was designed in a standard 0.35μm CMOS technology. A prototype has been fabricated by the Silicon Foundry AMS - Austria Micro Systems.