DocumentCode
2952398
Title
Modeling power budget requirements of implantable electronic devices
Author
Hashemi, S. ; Sawan, M. ; Savaria, Y.
Author_Institution
Polystim Neurotechnol. Lab., Ecole Polytech. de Montreal, Montreal, QC
fYear
2005
fDate
11-14 Dec. 2005
Firstpage
1
Lastpage
4
Abstract
We present in this paper a new analytical, empirical and behavioral modular model developed for accurate evaluation of power dissipation in a power conversion chain dedicated to power up an electronic implantable device. The model is suitable for power estimation/planning in early design stages, to determine the contribution of each circuit module on the total power consumption and to estimate the input and output voltages of each module. The model takes into account the influence of the dynamic and static losses. The parasitic capacitances associated with charge pump stages were also considered. The model demonstrates the dependence of power on several main design parameters. It is built based on average power consumption and is coded in Verilog-A. The model is flexible and robust to changes in design parameters and provides accurate and valid results over a wide range of parameter values.
Keywords
biomedical electronics; charge pump circuits; hardware description languages; prosthetics; Verilog-A; average power consumption; implantable electronic devices; parasitic capacitances; power budget requirements; power consumption; power conversion chain; power dissipation; power estimation-planning; Charge pumps; Circuits; Energy consumption; Hardware design languages; Implants; Parasitic capacitance; Power conversion; Power dissipation; Robustness; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronics, Circuits and Systems, 2005. ICECS 2005. 12th IEEE International Conference on
Conference_Location
Gammarth
Print_ISBN
978-9972-61-100-1
Electronic_ISBN
978-9972-61-100-1
Type
conf
DOI
10.1109/ICECS.2005.4633567
Filename
4633567
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