A High Throughput VLSI Architecture Design for H.264 Context-Based Adaptive Binary Arithmetic Decoding with Look Ahead Parsing

Author

Yang, Yao-Chang ; Lin, Chien-Chang ; Chang, Hsui-Cheng ; Su, Ching-Lung ; Guo, Jiun-In

Author_Institution

Dept. of Comput. Sci. & Inf. Eng., Nat. Chung Cheng Univ., Chia-Yi

fYear

2006

fDate

9-12 July 2006

Firstpage

357

Lastpage

360

Abstract

In this paper we present a high throughput VLSI architecture design for context-based adaptive binary arithmetic decoding (CABAD) in MPEG-4 AVC/H.264. To speed-up the inherent sequential operations in CABAD, we break down the processing bottleneck by proposing a look-ahead codeword parsing technique on the segmenting context tables with cache registers, which averagely reduces up to 53% of cycle count. Based on a 0.18 mum CMOS technology, the proposed design outperforms the existing design by both reducing 40% of hardware cost and achieving about 1.6 times data throughput at the same time

Keywords

VLSI; arithmetic codes; binary codes; cache storage; code standards; data compression; video coding; CABAD; MPEG-4 AVC-H.264; VLSI architecture design; cache register; context table segmenting; context-based adaptive binary arithmetic decoding; look-ahead codeword parsing technique; moving picture experts group; very large scale integration; Computer architecture; Costs; Decoding; Design engineering; Digital arithmetic; Hardware; MPEG standards; Throughput; Very large scale integration; Video coding;

fLanguage

English

Publisher

ieee

Conference_Titel

Multimedia and Expo, 2006 IEEE International Conference on

Conference_Location

Toronto, Ont.

Print_ISBN

1-4244-0366-7

Electronic_ISBN

1-4244-0367-7

Type

conf

DOI

10.1109/ICME.2006.262510

Filename

4036610